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| author | Thierry Reding <treding@nvidia.com> | 2019-07-26 12:16:18 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:30:05 +0100 |
| commit | 939e7430dee4e1c0595124b8ccd1c8b5db162dd8 (patch) | |
| tree | 08bbb96bbd9772d9a4255acc33f6e6fb8f3eedbd /block/blk-pm.h | |
| parent | 1aaa7698670cb980280e034d76f1bc1ca193af43 (diff) | |
| download | linux-939e7430dee4e1c0595124b8ccd1c8b5db162dd8.tar.bz2 | |
arm64: tegra: Fix base address for SOR1 on Tegra194
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'block/blk-pm.h')
0 files changed, 0 insertions, 0 deletions