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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-17 22:42:48 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-30 00:49:18 +0100 |
| commit | e761f6f332afe3356714a0d0eaf5ec1ebd8aab50 (patch) | |
| tree | 11a5bf3c2266f0d63c5bbd8def3e209fea9d091f /arch | |
| parent | 0074fb2c9e75acfdea391e6962c4be98444b4792 (diff) | |
| download | linux-e761f6f332afe3356714a0d0eaf5ec1ebd8aab50.tar.bz2 | |
ARM: l2c: highbank: remove explicit SMI call in L2 cache initialisation
Now that highbank uses the write_sec method, we don't need to enable
the L2 cache in SoC specific code; this can be done via the normal
mechanisms in the L2C code.
Checking with Rob Herring:
> > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means
> > l2x0_of_init() will see the L2 cache disabled, and will try to enable
> > it via the write_sec hook, so it should do the right thing.
>
> Yes, that should work. You should be able to just call l2x0_of_init
> unconditionally. The condition was really to just avoid the smc on
> Midway which does get handled on h/w, but not if running virtualized.
So also drop the DT check too. I'm leaving the config check in place
so that if L2 is disabled, the write_sec hook can be optimised away.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-highbank/highbank.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 4712aed3d9f6..245e588859ec 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -68,9 +68,7 @@ static void __init highbank_init_irq(void) highbank_scu_map_io(); /* Enable PL310 L2 Cache controller */ - if (IS_ENABLED(CONFIG_CACHE_L2X0) && - of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) { - highbank_smc1(0x102, 0x1); + if (IS_ENABLED(CONFIG_CACHE_L2X0)) { outer_cache.write_sec = highbank_l2c310_write_sec; l2x0_of_init(0, ~0); } |