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| author | David S. Miller <davem@davemloft.net> | 2009-11-05 20:24:33 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-11-05 20:24:33 -0800 |
| commit | 4eb0c00b6221f28b8988df37c9cb1bc5a2b91b39 (patch) | |
| tree | f1caf8f77980f74766c26e5bf1ce9a140fd17b2d /arch | |
| parent | 03717e3d12b625268848414e39beda25e4515692 (diff) | |
| download | linux-4eb0c00b6221f28b8988df37c9cb1bc5a2b91b39.tar.bz2 | |
sparc64: Add a comment about why we only use certain memory barriers these days.
Based upon feedback from Mathieu Desnoyers.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sparc/include/asm/system_64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad7..d47a98e66972 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h @@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ : : : "memory"); \ } while (0) +/* The kernel always executes in TSO memory model these days, + * and furthermore most sparc64 chips implement more stringent + * memory ordering than required by the specifications. + */ #define mb() membar_safe("#StoreLoad") #define rmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory") |