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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-08-22 14:04:41 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-08-22 14:04:41 -0700 |
commit | 433bcf67370bc170a345634aa1be4ee8ac905de9 (patch) | |
tree | f2a7afc2ccc3346515e8e12208f3b2bff4e84f33 /arch/xtensa/include/asm/pgtable.h | |
parent | b372115311942202346d93849991f07382783ef1 (diff) | |
parent | 35d231db53a60b76e218a56da30ad071d4717b56 (diff) | |
download | linux-433bcf67370bc170a345634aa1be4ee8ac905de9.tar.bz2 |
Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov:
- switch xtensa arch to the generic noncoherent direct mapping
operations
- add support for DMA_ATTR_NO_KERNEL_MAPPING attribute
- clean up users of platform/hardware.h in generic Xtensa code
- fix assembly cache maintenance code for long cache lines
- rework noMMU cache attributes initialization
- add big-endian HiFi2 test_kc705_be CPU variant
* tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: add test_kc705_be variant
xtensa: clean up boot-elf/bootstrap.S
xtensa: make bootparam parsing optional
xtensa: drop variant IRQ support
xtensa: drop unneeded platform/hardware.h headers
xtensa: move PLATFORM_NR_IRQS to Kconfig
xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START
xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE
xtensa: rework noMMU cache attributes initialization
xtensa: increase ranges in ___invalidate_{i,d}cache_all
xtensa: limit offsets in __loop_cache_{all,page}
xtensa: platform-specific handling of coherent memory
xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute
xtensa: use generic dma_noncoherent_ops
Diffstat (limited to 'arch/xtensa/include/asm/pgtable.h')
-rw-r--r-- | arch/xtensa/include/asm/pgtable.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h index 38802259978f..29cfe421cf41 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h @@ -66,6 +66,7 @@ #define FIRST_USER_ADDRESS 0UL #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) +#ifdef CONFIG_MMU /* * Virtual memory area. We keep a distance to other memory regions to be * on the safe side. We also use this area for cache aliasing. @@ -80,6 +81,13 @@ #define TLBTEMP_SIZE ICACHE_WAY_SIZE #endif +#else + +#define VMALLOC_START __XTENSA_UL_CONST(0) +#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff) + +#endif + /* * For the Xtensa architecture, the PTE layout is as follows: * |