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authorShanth Murthy <shanth.murthy@intel.com>2017-02-13 04:02:52 -0800
committerDarren Hart <dvhart@linux.intel.com>2017-02-24 23:48:46 -0800
commit76062b4ae2ea54fcfb8fce6940921a90f33f38da (patch)
treea31fec0f30185a87d7a26bb370c1bd8d5c842e3e /arch/x86
parent8e4b8c7d7df78a2c8fe4ba0daf12fc877f353f5c (diff)
downloadlinux-76062b4ae2ea54fcfb8fce6940921a90f33f38da.tar.bz2
platform/x86: intel_pmc_ipc: read s0ix residency API
This patch adds a new API to indicate S0ix residency in usec. It utilizes the PMC Global Control Registers (GCR) to read deep and shallow S0ix residency. PMC MMIO resources: o Lower 4kB: IPC1 (PMC inter-processor communication) interface o Upper 4kB: GCR (Global Control Registers) This enables the power management framework to take corrective actions when the platform fails to enter S0ix after kernel freeze as part of the suspend to idle flow. (echo freeze > /sys/power/state). This is expected to be used with a S0ix failsafe framework such as: <https://lwn.net/Articles/689505/> [rajneesh: folded in "fix division in 32-bit case" from Andy Shevchenko] Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Shanth Murthy <shanth.murthy@intel.com> [andy: fixed kbuild error, removed "total" from variables, fixed macro] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/include/asm/intel_pmc_ipc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h
index cd0310e186f4..4291b6a5ddf7 100644
--- a/arch/x86/include/asm/intel_pmc_ipc.h
+++ b/arch/x86/include/asm/intel_pmc_ipc.h
@@ -30,6 +30,7 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen, u32 dptr, u32 sptr);
int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen);
+int intel_pmc_s0ix_counter_read(u64 *data);
#else
@@ -50,6 +51,11 @@ static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
return -EINVAL;
}
+static inline int intel_pmc_s0ix_counter_read(u64 *data)
+{
+ return -EINVAL;
+}
+
#endif /*CONFIG_INTEL_PMC_IPC*/
#endif