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| author | Huacai Chen <chenhc@lemote.com> | 2018-09-05 17:33:08 +0800 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-10-15 23:11:14 -0700 |
| commit | d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea (patch) | |
| tree | eba25019a08b1bb9707cb00ce644ee73c75e9058 /arch/x86/power/cpu.c | |
| parent | 7f8502a539bbfca7c3027e0279060eb46dfde59f (diff) | |
| download | linux-d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea.tar.bz2 | |
MIPS: Loongson-3: Fix CPU UART irq delivery problem
Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
other CPUs) may cause interrupts be lost, especially in multi-package
machines (Package-0's UART irq cannot be delivered to others). So make
mask_loongson_irq() and unmask_loongson_irq() be no-ops.
The original problem (UART IRQ may deliver to any core) is also because
of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to
remove all of the stuff.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20433/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
Diffstat (limited to 'arch/x86/power/cpu.c')
0 files changed, 0 insertions, 0 deletions