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| author | Dave Airlie <airlied@redhat.com> | 2018-01-18 09:32:15 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2018-01-18 09:32:15 +1000 |
| commit | 4a6cc7a44e98a0460bd094b68c75f0705fdc450a (patch) | |
| tree | b8c86a1e0342b1166ab52c4d79e404eede57abec /arch/x86/lib/delay.c | |
| parent | 8563188e37b000979ab66521f4337df9a3453223 (diff) | |
| parent | a8750ddca918032d6349adbf9a4b6555e7db20da (diff) | |
| download | linux-4a6cc7a44e98a0460bd094b68c75f0705fdc450a.tar.bz2 | |
BackMerge tag 'v4.15-rc8' into drm-next
Linux 4.15-rc8
Daniel requested this for so the intel CI won't fall over on drm-next
so often.
Diffstat (limited to 'arch/x86/lib/delay.c')
| -rw-r--r-- | arch/x86/lib/delay.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index 553f8fd23cc4..4846eff7e4c8 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -107,10 +107,10 @@ static void delay_mwaitx(unsigned long __loops) delay = min_t(u64, MWAITX_MAX_LOOPS, loops); /* - * Use cpu_tss as a cacheline-aligned, seldomly + * Use cpu_tss_rw as a cacheline-aligned, seldomly * accessed per-cpu variable as the monitor target. */ - __monitorx(raw_cpu_ptr(&cpu_tss), 0, 0); + __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0); /* * AMD, like Intel, supports the EAX hint and EAX=0xf |