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| author | Peter Zijlstra <peterz@infradead.org> | 2022-03-08 16:30:35 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-03-15 10:32:39 +0100 |
| commit | 991625f3dd2cbc4b787deb0213e2bcf8fa264b21 (patch) | |
| tree | f328f63188d911d258d895b0f0a1a7d98ba16429 /arch/x86/kernel/idt.c | |
| parent | 0aec21cfb51bc1856206f312d8c13bf1f368d78e (diff) | |
| download | linux-991625f3dd2cbc4b787deb0213e2bcf8fa264b21.tar.bz2 | |
x86/ibt: Add IBT feature, MSR and #CP handling
The bits required to make the hardware go.. Of note is that, provided
the syscall entry points are covered with ENDBR, #CP doesn't need to
be an IST because we'll never hit the syscall gap.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org
Diffstat (limited to 'arch/x86/kernel/idt.c')
| -rw-r--r-- | arch/x86/kernel/idt.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 7676e3444c83..608eb63bf044 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -104,6 +104,10 @@ static const __initconst struct idt_data def_idts[] = { ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE), #endif +#ifdef CONFIG_X86_KERNEL_IBT + INTG(X86_TRAP_CP, asm_exc_control_protection), +#endif + #ifdef CONFIG_AMD_MEM_ENCRYPT ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC), #endif |