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author | Dave Airlie <airlied@redhat.com> | 2018-01-18 09:32:15 +1000 |
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committer | Dave Airlie <airlied@redhat.com> | 2018-01-18 09:32:15 +1000 |
commit | 4a6cc7a44e98a0460bd094b68c75f0705fdc450a (patch) | |
tree | b8c86a1e0342b1166ab52c4d79e404eede57abec /arch/x86/include/asm/intel_ds.h | |
parent | 8563188e37b000979ab66521f4337df9a3453223 (diff) | |
parent | a8750ddca918032d6349adbf9a4b6555e7db20da (diff) | |
download | linux-4a6cc7a44e98a0460bd094b68c75f0705fdc450a.tar.bz2 |
BackMerge tag 'v4.15-rc8' into drm-next
Linux 4.15-rc8
Daniel requested this for so the intel CI won't fall over on drm-next
so often.
Diffstat (limited to 'arch/x86/include/asm/intel_ds.h')
-rw-r--r-- | arch/x86/include/asm/intel_ds.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h new file mode 100644 index 000000000000..62a9f4966b42 --- /dev/null +++ b/arch/x86/include/asm/intel_ds.h @@ -0,0 +1,36 @@ +#ifndef _ASM_INTEL_DS_H +#define _ASM_INTEL_DS_H + +#include <linux/percpu-defs.h> + +#define BTS_BUFFER_SIZE (PAGE_SIZE << 4) +#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) + +/* The maximal number of PEBS events: */ +#define MAX_PEBS_EVENTS 8 + +/* + * A debug store configuration. + * + * We only support architectures that use 64bit fields. + */ +struct debug_store { + u64 bts_buffer_base; + u64 bts_index; + u64 bts_absolute_maximum; + u64 bts_interrupt_threshold; + u64 pebs_buffer_base; + u64 pebs_index; + u64 pebs_absolute_maximum; + u64 pebs_interrupt_threshold; + u64 pebs_event_reset[MAX_PEBS_EVENTS]; +} __aligned(PAGE_SIZE); + +DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); + +struct debug_store_buffers { + char bts_buffer[BTS_BUFFER_SIZE]; + char pebs_buffer[PEBS_BUFFER_SIZE]; +}; + +#endif |