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| author | Pu Wen <puwen@hygon.cn> | 2018-09-23 17:33:44 +0800 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2018-09-27 18:28:57 +0200 |
| commit | d4f7423efdd1419b17524d090ff9ff4024bcf09b (patch) | |
| tree | 860b9b06a3c15f693013d6a6453f6450c632a5b6 /arch/x86/include/asm/cacheinfo.h | |
| parent | 7eae653c8071e06719efc0b6e4da27d6908e5a5a (diff) | |
| download | linux-d4f7423efdd1419b17524d090ff9ff4024bcf09b.tar.bz2 | |
x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
The Hygon Dhyana CPU has a topology extensions bit in CPUID. With
this bit, the kernel can get the cache information. So add support in
cpuid4_cache_lookup_regs() to get the correct cache size.
The Hygon Dhyana CPU also discovers num_cache_leaves via CPUID leaf
0x8000001d, so add support to it in find_num_cache_leaves().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in the
same way as AMD does.
Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: bp@alien8.de
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Link: https://lkml.kernel.org/r/2a686b2ac0e2f5a1f2f5f101124d9dd44f949731.1537533369.git.puwen@hygon.cn
Diffstat (limited to 'arch/x86/include/asm/cacheinfo.h')
| -rw-r--r-- | arch/x86/include/asm/cacheinfo.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cacheinfo.h index e958e28f7ab5..86b63c7feab7 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -3,5 +3,6 @@ #define _ASM_X86_CACHEINFO_H void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id); #endif /* _ASM_X86_CACHEINFO_H */ |