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| author | Stephane Eranian <eranian@google.com> | 2020-10-01 06:57:49 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-10-29 11:00:39 +0100 |
| commit | 995f088efebe1eba0282a6ffa12411b37f8990c2 (patch) | |
| tree | 9e3185b05657e50aa991790dde6d74ba4dd8ee02 /arch/x86/events | |
| parent | 4cb6a42e4c4bc1902644eced67563e7405d4588e (diff) | |
| download | linux-995f088efebe1eba0282a6ffa12411b37f8990c2.tar.bz2 | |
perf/core: Add support for PERF_SAMPLE_CODE_PAGE_SIZE
When studying code layout, it is useful to capture the page size of the
sampled code address.
Add a new sample type for code page size.
The new sample type requires collecting the ip. The code page size can
be calculated from the NMI-safe perf_get_page_size().
For large PEBS, it's very unlikely that the mapping is gone for the
earlier PEBS records. Enable the feature for the large PEBS. The worst
case is that page-size '0' is returned.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201001135749.2804-5-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/perf_event.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index ee2b9b9fc2a5..10032f023fcc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -132,7 +132,7 @@ struct amd_nb { PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \ PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \ - PERF_SAMPLE_PERIOD) + PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE) #define PEBS_GP_REGS \ ((1ULL << PERF_REG_X86_AX) | \ |