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| author | Kan Liang <kan.liang@linux.intel.com> | 2021-04-12 07:30:46 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-04-19 20:03:25 +0200 |
| commit | d4b294bf84db7a84e295ddf19cb8e7f71b7bd045 (patch) | |
| tree | 15b788d9c4284746e953eaa452234dfe0b929d4c /arch/x86/events/perf_event.h | |
| parent | fc4b8fca2d8fc8aecd58508e81d55afe4ed76344 (diff) | |
| download | linux-d4b294bf84db7a84e295ddf19cb8e7f71b7bd045.tar.bz2 | |
perf/x86: Hybrid PMU support for counters
The number of GP and fixed counters are different among hybrid PMUs.
Each hybrid PMU should use its own counter related information.
When handling a certain hybrid PMU, apply the number of counters from
the corresponding hybrid PMU.
When reserving the counters in the initialization of a new event,
reserve all possible counters.
The number of counter recored in the global x86_pmu is for the
architecture counters which are available for all hybrid PMUs. KVM
doesn't support the hybrid PMU yet. Return the number of the
architecture counters for now.
For the functions only available for the old platforms, e.g.,
intel_pmu_drain_pebs_nhm(), nothing is changed.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-7-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/perf_event.h')
| -rw-r--r-- | arch/x86/events/perf_event.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 557c6746bc40..0539ad415750 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -635,6 +635,9 @@ struct x86_hybrid_pmu { struct pmu pmu; union perf_capabilities intel_cap; u64 intel_ctrl; + int max_pebs_events; + int num_counters; + int num_counters_fixed; }; static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) @@ -850,6 +853,7 @@ struct x86_pmu { * are available for all PMUs. The hybrid_pmu only includes the * unique capabilities. */ + int num_hybrid_pmus; struct x86_hybrid_pmu *hybrid_pmu; }; |