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authorChris Metcalf <cmetcalf@tilera.com>2013-09-13 10:57:54 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-09-13 10:57:54 -0400
commit4db30e38ec2ad937678964f227202c6b5e90508e (patch)
treeac07cd27dab9f895a9d83f61b99c3c3a78df4bf4 /arch/tile
parent399a946edbbe90bd03aec2e93ce58c9b3f18e70b (diff)
downloadlinux-4db30e38ec2ad937678964f227202c6b5e90508e.tar.bz2
tile: fix typos in comment in arch/tile/kernel/unaligned.c
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/kernel/unaligned.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/tile/kernel/unaligned.c b/arch/tile/kernel/unaligned.c
index b425fb6a480d..b030b4e78845 100644
--- a/arch/tile/kernel/unaligned.c
+++ b/arch/tile/kernel/unaligned.c
@@ -551,8 +551,8 @@ static tilegx_bundle_bits jit_x1_bnezt(int ra, int broff)
/*
* This function generates unalign fixup JIT.
*
- * We fist find unalign load/store instruction's destination, source
- * reguisters: ra, rb and rd. and 3 scratch registers by calling
+ * We first find unalign load/store instruction's destination, source
+ * registers: ra, rb and rd. and 3 scratch registers by calling
* find_regs(...). 3 scratch clobbers should not alias with any register
* used in the fault bundle. Then analyze the fault bundle to determine
* if it's a load or store, operand width, branch or address increment etc.