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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-08-02 11:15:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-08-22 09:46:03 +0200 |
| commit | 72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd (patch) | |
| tree | 84847dbad1e9774fa145e1d923746b406e4ef37f /arch/sparc | |
| parent | 13dec051c7f139eef345c55a60941843e72128f1 (diff) | |
| download | linux-72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd.tar.bz2 | |
arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types
As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/sparc')
0 files changed, 0 insertions, 0 deletions