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| author | Stuart Menefy <stuart.menefy@st.com> | 2007-11-30 17:06:36 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 13:18:59 +0900 |
| commit | cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93 (patch) | |
| tree | e60db5c0f3573558c97f39cfab78732220a72e6d /arch/sh/kernel/cpu/init.c | |
| parent | 325df7f20467da07901c4f2b006d3457bba0adec (diff) | |
| download | linux-cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93.tar.bz2 | |
sh: Preparation for uncached jumps through PMB.
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/init.c')
| -rw-r--r-- | arch/sh/kernel/cpu/init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index fd1688e6c61c..0f0c76a842e4 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -64,11 +64,11 @@ static void __init speculative_execution_init(void) * Generic first-level cache init */ #ifdef CONFIG_SUPERH32 -static void __init cache_init(void) +static void __uses_jump_to_uncached cache_init(void) { unsigned long ccr, flags; - jump_to_P2(); + jump_to_uncached(); ccr = ctrl_inl(CCR); /* @@ -145,7 +145,7 @@ static void __init cache_init(void) #endif ctrl_outl(flags, CCR); - back_to_P1(); + back_to_cached(); } #else #define cache_init() do { } while (0) |