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| author | Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> | 2017-04-09 15:00:21 -0700 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-04-28 21:51:28 +0300 |
| commit | 62a7b9c859d09af860c71cfbea4381061975ca72 (patch) | |
| tree | bdf4f62e5313716e8653057b6ab1a2d9a16ed212 /arch/score | |
| parent | 9d855d468dc655d10be6cb52e36aa0bbfa6f515d (diff) | |
| download | linux-62a7b9c859d09af860c71cfbea4381061975ca72.tar.bz2 | |
platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read
To maintain the uniformity in accessing GCR registers, this patch
modifies the S0ix counter read function to use GCR address base
instead of ipc address base.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Tested-by: Shanth Murthy <shanth.murthy@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/score')
0 files changed, 0 insertions, 0 deletions