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authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-09-20 15:04:11 +0200
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-10-19 10:59:57 +0200
commit73d3c44115514616ee9c4f356bb86d4426d0fc36 (patch)
tree0f02d41844cc10d399d6a1635621053c3727da2e /arch/riscv
parent20ce65bf89aab248886b80d1e7fa12277b2a0f2d (diff)
downloadlinux-73d3c44115514616ee9c4f356bb86d4426d0fc36.tar.bz2
riscv: dts: microchip: add missing compatibles for clint and plic
The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that also Core Local Interruptor and Platform-Level Interrupt Controller are coming from SiFive. Add proper compatibles to silence dtbs_check warnings: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint'] interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic'] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20210920130412.145231-1-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 9d2fbbc1f777..93730afe6c58 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -161,7 +161,7 @@
};
clint@2000000 {
- compatible = "sifive,clint0";
+ compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
@@ -172,7 +172,7 @@
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
- compatible = "sifive,plic-1.0.0";
+ compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <186>;
interrupt-controller;