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| author | Thomas Gleixner <tglx@linutronix.de> | 2019-05-06 12:04:12 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2019-05-06 12:04:12 +0200 |
| commit | fb4e0592654adb31bc6f3a738d6499b816a655d6 (patch) | |
| tree | e6edaf18cf3a7f49e93fb51de5a47f4b9e786f53 /arch/riscv/kernel/module.c | |
| parent | 471ba0e686cb13752bc1ff3216c54b69a2d250ea (diff) | |
| parent | 16e32c3cde7763ab875b9030b443ecbc8e352d8a (diff) | |
| download | linux-fb4e0592654adb31bc6f3a738d6499b816a655d6.tar.bz2 | |
Merge tag 'irqchip-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier
- The huge (and terrifying) TI INTR/INTA set of drivers
- Rewrite of the stm32mp1-exti driver as a platform driver
- Update the IOMMU MSI mapping API to be RT friendly
- A number of cleanups and other low impact fixes
Diffstat (limited to 'arch/riscv/kernel/module.c')
| -rw-r--r-- | arch/riscv/kernel/module.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7dd308129b40..2872edce894d 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -141,7 +141,7 @@ static int apply_r_riscv_hi20_rela(struct module *me, u32 *location, { s32 hi20; - if (IS_ENABLED(CMODEL_MEDLOW)) { + if (IS_ENABLED(CONFIG_CMODEL_MEDLOW)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n", me->name, (long long)v, location); |