diff options
| author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-08-04 10:23:19 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-13 08:31:31 -0700 |
| commit | 62b0194368147def8c5a77ce604a125d620fc582 (patch) | |
| tree | ffb0a3da4944a8aa15ce481a5e695acc03da3684 /arch/riscv/kernel/irq.c | |
| parent | 6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde (diff) | |
| download | linux-62b0194368147def8c5a77ce604a125d620fc582.tar.bz2 | |
clocksource: new RISC-V SBI timer driver
The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems. The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.
Contains various improvements from Atish Patra <atish.patra@wdc.com>.
Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
[hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
minor cleanups, merged hotplug cpu support and other improvements
from Atish]
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/irq.c')
| -rw-r--r-- | arch/riscv/kernel/irq.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index ab5f3e22c7cc..0cfac48a1272 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -30,6 +30,9 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs, unsigned long cause) irq_enter(); switch (cause & ~INTERRUPT_CAUSE_FLAG) { + case INTERRUPT_CAUSE_TIMER: + riscv_timer_interrupt(); + break; #ifdef CONFIG_SMP case INTERRUPT_CAUSE_SOFTWARE: /* |