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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:39:29 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:41:43 -0700 |
| commit | d26c4bbf992463c043fdee4b3e5efa3f08990862 (patch) | |
| tree | 6f7eb8b1da031352fc3e386dd4662fabf132b942 /arch/riscv/kernel/head.S | |
| parent | a6de21baf6373ac1ddd5c52e8fbd959f164ef9cf (diff) | |
| parent | 8b20d2db0a6d2761e0fc156eb74f7a55b92b3147 (diff) | |
| download | linux-d26c4bbf992463c043fdee4b3e5efa3f08990862.tar.bz2 | |
RISC-V: SMP cleanup and new features
This patch series now has evolved to contain several related changes.
1. Updated the assorted cleanup series by Palmer.
The original cleanup patch series can be found here.
http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html
2. Implemented decoupling linux logical CPU ids from hart id.
Some of the work has been inspired from ARM64.
Tested on QEMU & HighFive Unleashed board with/without SMP enabled.
3. Included Anup's cleanup and IPI stat patch.
All the patch series have been combined to avoid conflicts as a lot of
common code is changed different patch sets. Atish has mostly addressed
review comments and fixed checkpatch errors from Palmer's and Anup's
series.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/head.S')
| -rw-r--r-- | arch/riscv/kernel/head.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index c4d2c63f9a29..711190d473d4 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -47,6 +47,8 @@ ENTRY(_start) /* Save hart ID and DTB physical address */ mv s0, a0 mv s1, a1 + la a2, boot_cpu_hartid + REG_S a0, (a2) /* Initialize page tables and relocate to virtual addresses */ la sp, init_thread_union + THREAD_SIZE @@ -55,7 +57,7 @@ ENTRY(_start) /* Restore C environment */ la tp, init_task - sw s0, TASK_TI_CPU(tp) + sw zero, TASK_TI_CPU(tp) la sp, init_thread_union li a0, ASM_THREAD_SIZE |