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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2022-10-02 10:18:31 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-10-02 10:18:31 +0530 |
| commit | 122979aa26cd4a314aae889a0496eb829d50bc9e (patch) | |
| tree | eca6ea9de9f583ef7dc6556491b4191e339aa648 /arch/riscv/kernel/cpufeature.c | |
| parent | d837f19195e77f7c89b6645c8311f5ea6ff67905 (diff) | |
| download | linux-122979aa26cd4a314aae889a0496eb829d50bc9e.tar.bz2 | |
RISC-V: Probe Svinval extension form ISA string
Just like other ISA extensions, we allow callers/users to detect the
presence of Svinval extension from ISA string.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kernel/cpufeature.c')
| -rw-r--r-- | arch/riscv/kernel/cpufeature.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3b5583db9d80..9774f1271f93 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -204,6 +204,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); + SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); } #undef SET_ISA_EXT_MAP } |