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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:39:08 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-22 17:39:08 -0700 |
| commit | a6de21baf6373ac1ddd5c52e8fbd959f164ef9cf (patch) | |
| tree | b3071da1549139c260eb4db21728fc126f5f879f /arch/riscv/kernel/cpu.c | |
| parent | 4e4101cfefd382176b05356c5ef112561ae10384 (diff) | |
| parent | 827a438156e4c423b6875a092e272933952a2910 (diff) | |
| download | linux-a6de21baf6373ac1ddd5c52e8fbd959f164ef9cf.tar.bz2 | |
RISC-V: Fix some RV32 bugs and build failures
This patch set fixes up various failures in the RV32I port. The fixes
are all nominally independent, but are really only testable together
because the RV32I port fails to build without all of them. The patch
set includes:
* The removal of tishift on RV32I targets, as 128-bit integers are not
supported by the toolchain.
* The removal of swiotlb from RV32I targets, since all physical
addresses can be mapped by all hardware on all existing RV32I targets.
* The addition of ummodi3 and udivmoddi4 from an old version of GCC that
was licensed under GPLv2 as generic code, along with their use on
RV32I targets.
* A fix to our page alignment logic within ioremap for RV32I targets.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/cpu.c')
0 files changed, 0 insertions, 0 deletions