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| author | Cédric Le Goater <clg@kaod.org> | 2021-07-20 15:42:09 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-08-10 23:15:02 +1000 |
| commit | f5af0a978776b710f16dc99a85496b1e760bf9e0 (patch) | |
| tree | f11b8cfb23d59ceec4cc6718721f09d278481237 /arch/powerpc/platforms/cell | |
| parent | b68c6646cce5ee8caefa6333ee743f960222dcea (diff) | |
| download | linux-f5af0a978776b710f16dc99a85496b1e760bf9e0.tar.bz2 | |
KVM: PPC: Book3S HV: XIVE: Add support for automatic save-restore
On P10, the feature doing an automatic "save & restore" of a VCPU
interrupt context is set by default in OPAL. When a VP context is
pulled out, the state of the interrupt registers are saved by the XIVE
interrupt controller under the internal NVP structure representing the
VP. This saves a costly store/load in guest entries and exits.
If OPAL advertises the "save & restore" feature in the device tree,
it should also have set the 'H' bit in the CAM line. Check that when
vCPUs are connected to their ICP in KVM before going any further.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210720134209.256133-3-clg@kaod.org
Diffstat (limited to 'arch/powerpc/platforms/cell')
0 files changed, 0 insertions, 0 deletions