diff options
| author | Nick Child <nick.child@ibm.com> | 2021-12-16 17:00:18 -0500 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-12-23 22:33:11 +1100 |
| commit | c13f2b2bb5afd90f152c389c1c9245a0d43bce80 (patch) | |
| tree | dc55c6584f0818cecc50c3a3621982861e1e8067 /arch/powerpc/mm/nohash | |
| parent | ce0c6be9c69883df38e7631d1d7364b52f6db135 (diff) | |
| download | linux-c13f2b2bb5afd90f152c389c1c9245a0d43bce80.tar.bz2 | |
powerpc/mm: Add __init attribute to eligible functions
Some functions defined in 'arch/powerpc/mm' are deserving of an
`__init` macro attribute. These functions are only called by other
initialization functions and therefore should inherit the attribute.
Also, change function declarations in header files to include `__init`.
Signed-off-by: Nick Child <nick.child@ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211216220035.605465-4-nick.child@ibm.com
Diffstat (limited to 'arch/powerpc/mm/nohash')
| -rw-r--r-- | arch/powerpc/mm/nohash/44x.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/mm/nohash/fsl_book3e.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/mm/nohash/tlb.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/mm/nohash/44x.c b/arch/powerpc/mm/nohash/44x.c index 796c824acc8c..1beae802bb1c 100644 --- a/arch/powerpc/mm/nohash/44x.c +++ b/arch/powerpc/mm/nohash/44x.c @@ -38,7 +38,7 @@ int icache_44x_need_flush; unsigned long tlb_47x_boltmap[1024/8]; -static void ppc44x_update_tlb_hwater(void) +static void __init ppc44x_update_tlb_hwater(void) { /* The TLB miss handlers hard codes the watermark in a cmpli * instruction to improve performances rather than loading it @@ -122,7 +122,7 @@ static void __init ppc47x_update_boltmap(void) /* * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU */ -static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys) +static void __init ppc47x_pin_tlb(unsigned int virt, unsigned int phys) { unsigned int rA; int bolted; diff --git a/arch/powerpc/mm/nohash/fsl_book3e.c b/arch/powerpc/mm/nohash/fsl_book3e.c index 7f71bc3bf85f..dfe715e0f70a 100644 --- a/arch/powerpc/mm/nohash/fsl_book3e.c +++ b/arch/powerpc/mm/nohash/fsl_book3e.c @@ -259,7 +259,7 @@ void __init MMU_init_hw(void) flush_instruction_cache(); } -static unsigned long tlbcam_sz(int idx) +static unsigned long __init tlbcam_sz(int idx) { return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1; } diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c index 311281063d48..fd2c77af5c55 100644 --- a/arch/powerpc/mm/nohash/tlb.c +++ b/arch/powerpc/mm/nohash/tlb.c @@ -432,7 +432,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address) } } -static void setup_page_sizes(void) +static void __init setup_page_sizes(void) { unsigned int tlb0cfg; unsigned int tlb0ps; @@ -570,7 +570,7 @@ out: } } -static void setup_mmu_htw(void) +static void __init setup_mmu_htw(void) { /* * If we want to use HW tablewalk, enable it by patching the TLB miss |