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| author | Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2020-07-17 10:38:15 -0400 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-07-22 21:56:40 +1000 |
| commit | 9d4fc86dcd510dab5521a6c891f9bf379b85a7e0 (patch) | |
| tree | 7f885b485a5a633a65f94b79469afeb7619beec8 /arch/powerpc/include/asm/perf_event_server.h | |
| parent | 7e4a145e5b675d5a9182f756950f001eaa256795 (diff) | |
| download | linux-9d4fc86dcd510dab5521a6c891f9bf379b85a7e0.tar.bz2 | |
powerpc/perf: Update Power PMU cache_events to u64 type
Events of type PERF_TYPE_HW_CACHE was described for Power PMU
as: int (*cache_events)[type][op][result];
where type, op, result values unpacked from the event attribute config
value is used to generate the raw event code at runtime.
So far the event code values which used to create these cache-related
events were within 32 bit and `int` type worked. In power10,
some of the event codes are of 64-bit value and hence update the
Power PMU cache_events to `u64` type in `power_pmu` struct.
Also propagate this change to existing all PMU driver code paths
which are using ppmu->cache_events.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1594996707-3727-4-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'arch/powerpc/include/asm/perf_event_server.h')
| -rw-r--r-- | arch/powerpc/include/asm/perf_event_server.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h index f9a36680339d..14b8dc130598 100644 --- a/arch/powerpc/include/asm/perf_event_server.h +++ b/arch/powerpc/include/asm/perf_event_server.h @@ -53,7 +53,7 @@ struct power_pmu { const struct attribute_group **attr_groups; int n_generic; int *generic_events; - int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] + u64 (*cache_events)[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; |