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authorRalf Baechle <ralf@linux-mips.org>2006-10-07 19:44:33 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-10-08 02:38:28 +0100
commit937a801576f954bd030d7c4a5a94571710d87c0b (patch)
tree48d3440f765b56cf32a89b4b8193dd033d8227a8 /arch/mips/sni
parent31aa36658a123263a9a69896e348b9600e050679 (diff)
downloadlinux-937a801576f954bd030d7c4a5a94571710d87c0b.tar.bz2
[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sni')
-rw-r--r--arch/mips/sni/irq.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index cda165f42b6a..48fb74a7aaec 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -69,20 +69,20 @@ static struct irq_chip pciasic_irq_type = {
* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
* button interrupts. Later ...
*/
-static void pciasic_hwint0(struct pt_regs *regs)
+static void pciasic_hwint0(void)
{
panic("Received int0 but no handler yet ...");
}
/* This interrupt was used for the com1 console on the first prototypes. */
-static void pciasic_hwint2(struct pt_regs *regs)
+static void pciasic_hwint2(void)
{
/* I think this shouldn't happen on production machines. */
panic("hwint2 and no handler yet");
}
/* hwint5 is the r4k count / compare interrupt */
-static void pciasic_hwint5(struct pt_regs *regs)
+static void pciasic_hwint5(void)
{
panic("hwint5 and no handler yet");
}
@@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
*
* The EISA_INT bit in CSITPEND is high active, all others are low active.
*/
-static void pciasic_hwint1(struct pt_regs *regs)
+static void pciasic_hwint1(void)
{
u8 pend = *(volatile char *)PCIMT_CSITPEND;
unsigned long flags;
@@ -119,13 +119,13 @@ static void pciasic_hwint1(struct pt_regs *regs)
if (unlikely(irq < 0))
return;
- do_IRQ(irq, regs);
+ do_IRQ(irq);
}
if (!(pend & IT_SCSI)) {
flags = read_c0_status();
clear_c0_status(ST0_IM);
- do_IRQ(PCIMT_IRQ_SCSI, regs);
+ do_IRQ(PCIMT_IRQ_SCSI);
write_c0_status(flags);
}
}
@@ -133,7 +133,7 @@ static void pciasic_hwint1(struct pt_regs *regs)
/*
* hwint 3 should deal with the PCI A - D interrupts,
*/
-static void pciasic_hwint3(struct pt_regs *regs)
+static void pciasic_hwint3(void)
{
u8 pend = *(volatile char *)PCIMT_CSITPEND;
int irq;
@@ -141,21 +141,21 @@ static void pciasic_hwint3(struct pt_regs *regs)
pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
clear_c0_status(IE_IRQ3);
irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
- do_IRQ(irq, regs);
+ do_IRQ(irq);
set_c0_status(IE_IRQ3);
}
/*
* hwint 4 is used for only the onboard PCnet 32.
*/
-static void pciasic_hwint4(struct pt_regs *regs)
+static void pciasic_hwint4(void)
{
clear_c0_status(IE_IRQ4);
- do_IRQ(PCIMT_IRQ_ETHERNET, regs);
+ do_IRQ(PCIMT_IRQ_ETHERNET);
set_c0_status(IE_IRQ4);
}
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
static unsigned char led_cache;
@@ -163,17 +163,17 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
*(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
if (pending & 0x0800)
- pciasic_hwint1(regs);
+ pciasic_hwint1();
else if (pending & 0x4000)
- pciasic_hwint4(regs);
+ pciasic_hwint4();
else if (pending & 0x2000)
- pciasic_hwint3(regs);
+ pciasic_hwint3();
else if (pending & 0x1000)
- pciasic_hwint2(regs);
+ pciasic_hwint2();
else if (pending & 0x8000)
- pciasic_hwint5(regs);
+ pciasic_hwint5();
else if (pending & 0x0400)
- pciasic_hwint0(regs);
+ pciasic_hwint0();
}
void __init init_pciasic(void)