diff options
| author | Sashka Nochkin <linux-mips@durdom.com> | 2016-04-19 23:44:45 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:39:43 +0200 |
| commit | 86ce9a340e38bcba664fb11c7ab9ba03fcf5e55e (patch) | |
| tree | 8d684c0d73575e19f1e5a93721af2c513c142d0e /arch/mips/ralink | |
| parent | 6533af4d4831c421cd9aa4dce7cfc19a3514cc09 (diff) | |
| download | linux-86ce9a340e38bcba664fb11c7ab9ba03fcf5e55e.tar.bz2 | |
mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type
Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used.
However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM.
The patch below reflects that.
Signed-off-by: Sashka Nochkin <linux-mips@durdom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink')
| -rw-r--r-- | arch/mips/ralink/mt7620.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 2c623f6bca08..88b82fe21ae6 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -581,11 +581,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); - if (is_mt76x8()) + if (is_mt76x8()) { dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; - else + } else { dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; + if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) + dram_type = SYSCFG0_DRAM_TYPE_SDRAM; + } soc_info->mem_base = MT7620_DRAM_BASE; if (is_mt76x8()) |