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authorKevin Hilman <khilman@linaro.org>2013-08-14 08:14:50 -0700
committerKevin Hilman <khilman@linaro.org>2013-08-14 08:14:50 -0700
commit080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047 (patch)
tree2a367e97dcffe9ced54ff71b03ab893a3248fdb4 /arch/mips/lib/uncached.c
parente91f24ae027a583f2faff84456fa2630144bfed8 (diff)
parent39c41df9c1950fba0ee6a4e7a63be281e89fe437 (diff)
downloadlinux-080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047.tar.bz2
Merge branch 'zynq/dt' into next/dt
* zynq/dt: (1054 commits) arm: zynq: dt: Set correct L2 ram latencies + v3.11-rc5 Conflicts: arch/arm/Makefile
Diffstat (limited to 'arch/mips/lib/uncached.c')
-rw-r--r--arch/mips/lib/uncached.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 65e3dfc4e585..d8522f8e842a 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -36,7 +36,7 @@
* values, so we can avoid sharing the same stack area between a cached
* and the uncached mode.
*/
-unsigned long __cpuinit run_uncached(void *func)
+unsigned long run_uncached(void *func)
{
register long sp __asm__("$sp");
register long ret __asm__("$2");