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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2022-11-07 18:05:56 -0800 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2022-11-14 09:58:31 -0800 |
| commit | 016241168dc550b1a99fd6a85066e9960a94f610 (patch) | |
| tree | c5e49f7af1694193cd116018ee5a084345870b67 /arch/mips/lantiq/prom.c | |
| parent | 9deca798362e22608a2729d50ce7db74b3698b32 (diff) | |
| download | linux-016241168dc550b1a99fd6a85066e9960a94f610.tar.bz2 | |
drm/i915/uc: use different ggtt pin offsets for uc loads
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On MTL, however, this can happen if both
GTs are reset at the same time, so we can't pin everything in the same
spot and we need to use separate offset. For simplicity, instead of
calculating the exact required size, we reserve a 2MB slot for each fw.
v2: fail fetch if FW is > 2MBs, improve comments (John)
v3: more comment improvements (John)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <john.c.harrison@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221108020600.3575467-3-daniele.ceraolospurio@intel.com
Diffstat (limited to 'arch/mips/lantiq/prom.c')
0 files changed, 0 insertions, 0 deletions