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authorMatt Redfearn <matt.redfearn@imgtec.com>2016-09-07 10:45:12 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-10-04 16:13:57 +0200
commitf6b43d935482abe28e9206ad10e1d2aa3fc78996 (patch)
tree08e3a1a259bba1962258df89cff43d9a0ea9036f /arch/mips/kernel
parentb97d0b9099afcd5c569acaf9b0eb3f6e3b1b1f35 (diff)
downloadlinux-f6b43d935482abe28e9206ad10e1d2aa3fc78996.tar.bz2
MIPS: pm-cps: Update comments on barrier instructions
This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Kees Cook <keescook@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14220/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/pm-cps.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 2faa227a032e..7e8d4aa22233 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -315,7 +315,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
i * line_size * line_stride, t0);
}
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(pp, stype_memory);
uasm_i_ehb(pp);
@@ -414,7 +414,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_il_beqz(&p, &r, t2, lbl_incready);
uasm_i_addiu(&p, t1, t1, 1);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
/*
@@ -467,7 +467,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
Index_Writeback_Inv_D, lbl_flushdcache);
- /* Completion barrier */
+ /* Barrier ensuring previous cache invalidates are complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
@@ -480,7 +480,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Sync to ensure previous interventions are complete */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_intervention);
uasm_i_ehb(&p);
@@ -526,7 +526,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
goto gen_done;
}
- /* Completion barrier */
+ /* Barrier to ensure write to CPC command is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
}
@@ -561,7 +561,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
- /* Completion barrier */
+ /* Barrier to ensure write to coherence control is complete */
uasm_i_sync(&p, stype_memory);
uasm_i_ehb(&p);
@@ -575,7 +575,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_il_beqz(&p, &r, t2, lbl_decready);
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}
@@ -597,7 +597,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
*/
uasm_build_label(&l, p, lbl_secondary_cont);
- /* Ordering barrier */
+ /* Barrier ensuring all CPUs see the updated r_nc_count value */
uasm_i_sync(&p, stype_ordering);
}