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authorMatt Redfearn <matt.redfearn@imgtec.com>2016-09-07 10:45:15 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-10-04 16:13:57 +0200
commit90b084b1bc7ebde5379017c29ae617fcc4ccd557 (patch)
treea3df59f05a5633a374c5dc5021ea80cfdfd86744 /arch/mips/kernel
parent85e540be7549c8eda90f056d30534be8f58777a7 (diff)
downloadlinux-90b084b1bc7ebde5379017c29ae617fcc4ccd557.tar.bz2
MIPS: pm-cps: Use MIPS standard completion barrier
SYNC type 0 is defined in the MIPS architecture as a completion barrier where all loads/stores in the pipeline before the sync instruction must complete before any loads/stores subsequent to the sync instruction. In places where we require loads / stores be globally completed, use the standard completion sync stype. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/pm-cps.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index d7037fe00d1c..953ff0db9061 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -315,7 +315,7 @@ static int __init cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
}
/* Barrier ensuring previous cache invalidates are complete */
- uasm_i_sync(pp, stype_memory);
+ uasm_i_sync(pp, STYPE_SYNC);
uasm_i_ehb(pp);
/* Check whether the pipeline stalled due to the FSB being full */
@@ -467,7 +467,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
Index_Writeback_Inv_D, lbl_flushdcache);
/* Barrier ensuring previous cache invalidates are complete */
- uasm_i_sync(&p, stype_memory);
+ uasm_i_sync(&p, STYPE_SYNC);
uasm_i_ehb(&p);
/*
@@ -480,7 +480,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_lw(&p, t0, 0, r_pcohctl);
/* Barrier to ensure write to coherence control is complete */
- uasm_i_sync(&p, stype_intervention);
+ uasm_i_sync(&p, STYPE_SYNC);
uasm_i_ehb(&p);
/* Disable coherence */
@@ -526,7 +526,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
}
/* Barrier to ensure write to CPC command is complete */
- uasm_i_sync(&p, stype_memory);
+ uasm_i_sync(&p, STYPE_SYNC);
uasm_i_ehb(&p);
}
@@ -561,7 +561,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_lw(&p, t0, 0, r_pcohctl);
/* Barrier to ensure write to coherence control is complete */
- uasm_i_sync(&p, stype_memory);
+ uasm_i_sync(&p, STYPE_SYNC);
uasm_i_ehb(&p);
if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {