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authorJulia Lawall <Julia.Lawall@inria.fr>2022-04-30 21:03:10 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2022-05-04 22:22:59 +0200
commit94bd83e45acdd72b81545ff25324a13bc5cae54e (patch)
tree3f5d2f5e98d180d44794feb43cb3f1d9418b8200 /arch/mips/kernel/perf_event_mipsxx.c
parent7671f9674b474505de289b548206ef48b0f5ceac (diff)
downloadlinux-94bd83e45acdd72b81545ff25324a13bc5cae54e.tar.bz2
MIPS: fix typos in comments
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/perf_event_mipsxx.c')
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 1641d274fe37..c4d6b09136b1 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -329,7 +329,7 @@ static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
for (i = mipspmu.num_counters - 1; i >= 0; i--) {
/*
* Note that some MIPS perf events can be counted by both
- * even and odd counters, wheresas many other are only by
+ * even and odd counters, whereas many other are only by
* even _or_ odd counters. This introduces an issue that
* when the former kind of event takes the counter the
* latter kind of event wants to use, then the "counter