summaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/cevt-r4k.c
diff options
context:
space:
mode:
authorSteven J. Hill <sjhill@mips.com>2012-08-31 16:18:49 -0500
committerSteven J. Hill <sjhill@mips.com>2012-09-13 15:43:49 -0500
commit98b67c37db336446fa3a543654c012680bbe2291 (patch)
tree53815c5db2034cf33de82364bea99302221f786f /arch/mips/kernel/cevt-r4k.c
parent2299c49d601c20ba502f5cc7b2f72a0048f485db (diff)
downloadlinux-98b67c37db336446fa3a543654c012680bbe2291.tar.bz2
MIPS: Add EIC support for GIC.
Add support to use an external interrupt controller with the GIC. Signed-off-by: Steven J. Hill <sjhill@mips.com>
Diffstat (limited to 'arch/mips/kernel/cevt-r4k.c')
-rw-r--r--arch/mips/kernel/cevt-r4k.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9599d..75323925e537 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,7 @@
#include <asm/smtc_ipi.h>
#include <asm/time.h>
#include <asm/cevt-r4k.h>
+#include <asm/gic.h>
/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
@@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev)
*/
static int c0_compare_int_pending(void)
{
+#ifdef CONFIG_IRQ_GIC
+ if (cpu_has_veic)
+ return gic_get_timer_pending();
+#endif
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}