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| author | Florian Fainelli <f.fainelli@gmail.com> | 2016-02-03 18:14:50 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-09 12:00:01 +0200 |
| commit | 21b30c00f3067001519eda166675c1958b163c91 (patch) | |
| tree | 63490d6444a3240daa23cdbe3b4dde7d117fa64e /arch/mips/kernel/bmips_vec.S | |
| parent | cbbda6e7c9c3e4532bd70a73ff9d5e6655c894dc (diff) | |
| download | linux-21b30c00f3067001519eda166675c1958b163c91.tar.bz2 | |
MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization code
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this
would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX
and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor
id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to
bring them online.
Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some
additional changes in the L1 interrupt area to work properly with interrupt
affinity.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/12377/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/bmips_vec.S')
| -rw-r--r-- | arch/mips/kernel/bmips_vec.S | 41 |
1 files changed, 38 insertions, 3 deletions
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S index d9495f3f3fad..921a5fa55da6 100644 --- a/arch/mips/kernel/bmips_vec.S +++ b/arch/mips/kernel/bmips_vec.S @@ -88,7 +88,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) li k1, (1 << 19) mfc0 k0, CP0_STATUS and k0, k1 - beqz k0, bmips_smp_entry + beqz k0, soft_reset #if defined(CONFIG_CPU_BMIPS5000) mfc0 k0, CP0_PRID @@ -126,13 +126,48 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) .set arch=r4000 eret +#ifdef CONFIG_SMP +soft_reset: + +#if defined(CONFIG_CPU_BMIPS5000) + mfc0 k0, CP0_PRID + andi k0, 0xff00 + li k1, PRID_IMP_BMIPS5200 + bne k0, k1, bmips_smp_entry + + /* if running on TP 1, jump to bmips_smp_entry */ + mfc0 k0, $22 + li k1, (1 << 24) + and k1, k0 + bnez k1, bmips_smp_entry + nop + + /* + * running on TP0, can not be core 0 (the boot core). + * Check for soft reset. Indicates a warm boot + */ + mfc0 k0, $12 + li k1, (1 << 20) + and k0, k1 + beqz k0, bmips_smp_entry + + /* + * Warm boot. + * Cache init is only done on TP0 + */ + la k0, bmips_5xxx_init + jalr k0 + nop + + b bmips_smp_entry + nop +#endif + /*********************************************************************** * CPU1 reset vector (used for the initial boot only) * This is still part of bmips_reset_nmi_vec(). ***********************************************************************/ -#ifdef CONFIG_SMP - bmips_smp_entry: /* set up CP0 STATUS; enable FPU */ |