diff options
| author | Lars-Peter Clausen <lars@metafoo.de> | 2011-03-23 21:08:54 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 18:45:16 +0100 |
| commit | cd11d14de91809ff3a150f823965a5b4209cad84 (patch) | |
| tree | a356da8a0d39d508fd61a65da46179e5b2d1411a /arch/mips/jz4740 | |
| parent | 42b64f388c171a7a1a8962d93d9bae2c04da7738 (diff) | |
| download | linux-cd11d14de91809ff3a150f823965a5b4209cad84.tar.bz2 | |
MIPS: JZ4740: GPIO: Use shared irq chip for all gpios
Currently there is one irq_chip per gpio_chip with the only difference
being the name. Since the information whether the irq belong to GPIO
bank A, B, C or D is not that important rewrite the code to simply use
a single irq_chip for all gpio_chips.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2182/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/jz4740')
| -rw-r--r-- | arch/mips/jz4740/gpio.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index 1e28b758de1f..9bb0770fa76e 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c @@ -86,7 +86,6 @@ struct jz_gpio_chip { spinlock_t lock; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; struct sys_device sysdev; }; @@ -435,6 +434,17 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } +static struct irq_chip jz_gpio_irq_chip = { + .name = "GPIO", + .irq_mask = jz_gpio_irq_mask, + .irq_unmask = jz_gpio_irq_unmask, + .irq_ack = jz_gpio_irq_ack, + .irq_startup = jz_gpio_irq_startup, + .irq_shutdown = jz_gpio_irq_shutdown, + .irq_set_type = jz_gpio_irq_set_type, + .irq_set_wake = jz_gpio_irq_set_wake, +}; + /* * This lock class tells lockdep that GPIO irqs are in a different * category than their parents, so it won't report false recursion. @@ -453,16 +463,6 @@ static struct lock_class_key gpio_lock_class; .base = JZ4740_GPIO_BASE_ ## _bank, \ .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ }, \ - .irq_chip = { \ - .name = "GPIO Bank " # _bank, \ - .irq_mask = jz_gpio_irq_mask, \ - .irq_unmask = jz_gpio_irq_unmask, \ - .irq_ack = jz_gpio_irq_ack, \ - .irq_startup = jz_gpio_irq_startup, \ - .irq_shutdown = jz_gpio_irq_shutdown, \ - .irq_set_type = jz_gpio_irq_set_type, \ - .irq_set_wake = jz_gpio_irq_set_wake, \ - }, \ } static struct jz_gpio_chip jz4740_gpio_chips[] = { @@ -529,7 +529,8 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); set_irq_chip_data(irq, chip); - set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); + set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, + handle_level_irq); } return 0; |