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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-05-16 15:39:23 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-05-16 15:39:23 +0200
commitd6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f (patch)
treec757e3701fbe9dbbf35525e980bd155c244cce52 /arch/mips/include
parent4419da5d5d4b1788568b7bf22c083ba2832891df (diff)
parent42226c989789d8da4af1de0c31070c96726d990c (diff)
downloadlinux-d6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f.tar.bz2
Merge 5.18-rc7 into usb-next
We need the tty fixes in here as well, as we need to revert one of them :( Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/timex.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index b05bb70a2e46..8026baf46e72 100644
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -40,9 +40,9 @@
typedef unsigned int cycles_t;
/*
- * On R4000/R4400 before version 5.0 an erratum exists such that if the
- * cycle counter is read in the exact moment that it is matching the
- * compare register, no interrupt will be generated.
+ * On R4000/R4400 an erratum exists such that if the cycle counter is
+ * read in the exact moment that it is matching the compare register,
+ * no interrupt will be generated.
*
* There is a suggested workaround and also the erratum can't strike if
* the compare interrupt isn't being used as the clock source device.
@@ -63,7 +63,7 @@ static inline int can_use_mips_counter(unsigned int prid)
if (!__builtin_constant_p(cpu_has_counter))
asm volatile("" : "=m" (cpu_data[0].options));
if (likely(cpu_has_counter &&
- prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0))))
+ prid > (PRID_IMP_R4000 | PRID_REV_ENCODE_44(15, 15))))
return 1;
else
return 0;