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| author | Paul Cercueil <paul@crapouillou.net> | 2020-09-06 21:29:22 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-18 16:26:36 +0200 |
| commit | 95b1f6db67aea9135b018497f7ed4446a060cba2 (patch) | |
| tree | ff4f377e6be5465abbc321244069f8da30d016f2 /arch/mips/include/asm | |
| parent | 7487abbe85afd02c35c283315cefc5e19c28d40f (diff) | |
| download | linux-95b1f6db67aea9135b018497f7ed4446a060cba2.tar.bz2 | |
MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.
Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/pgtable-bits.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index e26dc41a8a68..2362842ee2b5 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -249,11 +249,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) -#elif defined(CONFIG_MACH_INGENIC) - -/* Ingenic uses the WA bit to achieve write-combine memory writes */ -#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) - #endif #ifndef _CACHE_CACHABLE_NO_WA |