diff options
author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:45 +0200 |
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committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:48 +0200 |
commit | 44def3426e4ac5a2dbdb5c8304397f4daa38eb2f (patch) | |
tree | 365e80bb0639308afa9500270f69b83fdd6f0d3b /arch/mips/include/asm | |
parent | 5e5b6527128cea50f12a7064bf61b130b3a2739a (diff) | |
download | linux-44def3426e4ac5a2dbdb5c8304397f4daa38eb2f.tar.bz2 |
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-generic/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip22/war.h | 5 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip27/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip28/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip30/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ip32/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-malta/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-rc32434/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-rm/war.h | 5 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-sibyte/war.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-tx49xx/war.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/war.h | 15 |
13 files changed, 0 insertions, 36 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h index 915ce0352c20..4bc396d0fdd9 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/war.h +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -9,7 +9,6 @@ #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h index 44d14be2e1e5..4d46a880b832 100644 --- a/arch/mips/include/asm/mach-generic/war.h +++ b/arch/mips/include/asm/mach-generic/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MACH_GENERIC_WAR_H #define __ASM_MACH_GENERIC_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h index 9154c54d428a..a5a1c41df74e 100644 --- a/arch/mips/include/asm/mach-ip22/war.h +++ b/arch/mips/include/asm/mach-ip22/war.h @@ -8,11 +8,6 @@ #ifndef __ASM_MIPS_MACH_IP22_WAR_H #define __ASM_MIPS_MACH_IP22_WAR_H -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ - -#define R4600_V2_HIT_CACHEOP_WAR 1 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h index e7c070c85b7c..5891d506cffd 100644 --- a/arch/mips/include/asm/mach-ip27/war.h +++ b/arch/mips/include/asm/mach-ip27/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_IP27_WAR_H #define __ASM_MIPS_MACH_IP27_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h index 22d9f78bf552..346fc567ebb3 100644 --- a/arch/mips/include/asm/mach-ip28/war.h +++ b/arch/mips/include/asm/mach-ip28/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_IP28_WAR_H #define __ASM_MIPS_MACH_IP28_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h index 1400b030982e..f887a0a53e18 100644 --- a/arch/mips/include/asm/mach-ip30/war.h +++ b/arch/mips/include/asm/mach-ip30/war.h @@ -5,7 +5,6 @@ #ifndef __ASM_MIPS_MACH_IP30_WAR_H #define __ASM_MIPS_MACH_IP30_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h index f91f4eddce8f..980dbd34355c 100644 --- a/arch/mips/include/asm/mach-ip32/war.h +++ b/arch/mips/include/asm/mach-ip32/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_IP32_WAR_H #define __ASM_MIPS_MACH_IP32_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h index a4d5d0926e81..29f56803e3e5 100644 --- a/arch/mips/include/asm/mach-malta/war.h +++ b/arch/mips/include/asm/mach-malta/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_MIPS_WAR_H #define __ASM_MIPS_MACH_MIPS_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 1 diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h index 82ce2d313eed..749787bb6c8e 100644 --- a/arch/mips/include/asm/mach-rc32434/war.h +++ b/arch/mips/include/asm/mach-rc32434/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_MIPS_WAR_H #define __ASM_MIPS_MACH_MIPS_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 1 diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h index 192ec3358ad0..aded634ccb01 100644 --- a/arch/mips/include/asm/mach-rm/war.h +++ b/arch/mips/include/asm/mach-rm/war.h @@ -8,11 +8,6 @@ #ifndef __ASM_MIPS_MACH_RM_WAR_H #define __ASM_MIPS_MACH_RM_WAR_H -/* - * The RM200C seems to have been shipped only with V2.0 R4600s - */ - -#define R4600_V2_HIT_CACHEOP_WAR 1 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index bf793d36c890..78fd2ad4930b 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -8,8 +8,6 @@ #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H #define __ASM_MIPS_MACH_SIBYTE_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 - #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS) #ifndef __ASSEMBLY__ diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h index 7da1a3ea54c7..0b1666e0391a 100644 --- a/arch/mips/include/asm/mach-tx49xx/war.h +++ b/arch/mips/include/asm/mach-tx49xx/war.h @@ -8,7 +8,6 @@ #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H #define __ASM_MIPS_MACH_TX49XX_WAR_H -#define R4600_V2_HIT_CACHEOP_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0 diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index d336a0e57093..37092c2c68e1 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -73,21 +73,6 @@ #endif /* - * Writeback and invalidate the primary cache dcache before DMA. - * - * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, - * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These - * CACHE instructions should be separated from any potential data cache miss - * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on https://www.idt.com/ - * in .pdf format.) - */ -#ifndef R4600_V2_HIT_CACHEOP_WAR -#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform -#endif - -/* * Workaround for the Sibyte M3 errata the text of which can be found at * * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt |