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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-12-03 12:37:32 +0000 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 15:37:37 +0000 |
| commit | 7c151d3d5d7a032e08dbe86ad6088622391bf13e (patch) | |
| tree | 362d5ffcf8fea7c26373750efb106ca1e41c275f /arch/mips/include/asm/thread_info.h | |
| parent | b0a668fb2038d846a466c7a16a358d874002b697 (diff) | |
| download | linux-7c151d3d5d7a032e08dbe86ad6088622391bf13e.tar.bz2 | |
MIPS: Make use of the ERETNC instruction on MIPS R6
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
one, except it does not clear the LLB bit in the LLADDR register.
This feature is necessary to safely emulate R2 LL/SC instructions.
However, on context switches, we need to clear the LLAddr/LLB bit
in order to make sure that an SC instruction from the new thread
will never succeed if it happens to interrupt an LL operation on the
same address from the previous thread.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/thread_info.h')
| -rw-r--r-- | arch/mips/include/asm/thread_info.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 99eea59604e9..fb68fd2714fb 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -28,7 +28,7 @@ struct thread_info { unsigned long tp_value; /* thread pointer */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ - + int r2_emul_return; /* 1 => Returning from R2 emulator */ mm_segment_t addr_limit; /* * thread address space limit: * 0x7fffffff for user-thead |