diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-08-26 15:17:34 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-10-05 01:31:20 +0200 |
| commit | b6d5e47e67292542a41c3fe367bacb364eb4e601 (patch) | |
| tree | 009d252825c827993b2b6fb67b21827cb1fc20a4 /arch/mips/include/asm/mips-boards | |
| parent | 0a15273666aa18a45985e6419afa05ec24ecfeb4 (diff) | |
| download | linux-b6d5e47e67292542a41c3fe367bacb364eb4e601.tar.bz2 | |
MIPS: SEAD3: Probe interrupt controllers using DT
Probe the CPU interrupt controller & optional Global Interrupt
Controller (GIC) using devicetree rather than platform code. Because the
bootloader on SEAD3 does not provide a device tree to the kernel & the
device tree is always built in, we patch out the GIC node during boot if
we detect that a GIC is not present in the system.
The appropriate IRQ domain is discovered by platform code setting up
device IRQ numbers temporarily. It will be removed by further patches
which move the devices towards being probed via device tree.
No behavioural change is intended by this patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: Jacek Anaszewski <j.anaszewski@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14047/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mips-boards')
| -rw-r--r-- | arch/mips/include/asm/mips-boards/sead3int.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 8932c7de0419..bd85da3d6770 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -12,12 +12,7 @@ #include <linux/irqchip/mips-gic.h> -/* SEAD-3 GIC address space definitions. */ -#define GIC_BASE_ADDR 0x1b1c0000 -#define GIC_ADDRSPACE_SZ (128 * 1024) - /* CPU interrupt offsets */ -#define CPU_INT_GIC 2 #define CPU_INT_EHCI 2 #define CPU_INT_UART0 4 #define CPU_INT_UART1 4 |