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| author | Chuanhong Guo <gch981213@gmail.com> | 2021-03-26 22:38:40 -0700 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-03-29 11:18:54 +0200 |
| commit | 139c949f7f0ac0dd1c0da132675be80e6d76c65d (patch) | |
| tree | 85e70d4b58eff856d28892db0f7274acc1511827 /arch/mips/include/asm/mach-ralink/mt7621.h | |
| parent | 8eb6eb4882f2eb3ed516484bdde7db359785b6df (diff) | |
| download | linux-139c949f7f0ac0dd1c0da132675be80e6d76c65d.tar.bz2 | |
MIPS: ralink: mt7621: add memory detection support
mt7621 has the following memory map:
0x0-0x1c000000: lower 448m memory
0x1c000000-0x2000000: peripheral registers
0x20000000-0x2400000: higher 64m memory
detect_memory_region in arch/mips/kernel/setup.c only adds the first
memory region and isn't suitable for 512m memory detection because
it may accidentally read the memory area for peripheral registers.
This commit adds memory detection capability for mt7621:
1. Add the highmem area when 512m is detected.
2. Guard memcmp from accessing peripheral registers:
This only happens when a user decided to change kernel load address
to 256m or higher address. Since this is a quite unusual case, we
just skip 512m testing and return 256m as memory size.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Minor commit message reword, make mt7621_memory_detect static]
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ralink/mt7621.h')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7621.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h index e1af1ba50bd8..6bbf082dd149 100644 --- a/arch/mips/include/asm/mach-ralink/mt7621.h +++ b/arch/mips/include/asm/mach-ralink/mt7621.h @@ -24,9 +24,10 @@ #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf -#define MT7621_DRAM_BASE 0x0 -#define MT7621_DDR2_SIZE_MIN 32 -#define MT7621_DDR2_SIZE_MAX 256 +#define MT7621_LOWMEM_BASE 0x0 +#define MT7621_LOWMEM_MAX_SIZE 0x1C000000 +#define MT7621_HIGHMEM_BASE 0x20000000 +#define MT7621_HIGHMEM_SIZE 0x4000000 #define MT7621_CHIP_NAME0 0x3637544D #define MT7621_CHIP_NAME1 0x20203132 |