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authorMaciej W. Rozycki <macro@linux-mips.org>2013-09-17 16:58:10 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-09-18 20:25:19 +0200
commit8ff374b9c296b96484d5e63b45b22d0862ffee8f (patch)
tree0a40c8b881b985854a58793b14ca7b4de9c6f123 /arch/mips/include/asm/mach-au1x00
parentb42b4f3af8b1ac2f7b09781d523bf918f366d8d6 (diff)
downloadlinux-8ff374b9c296b96484d5e63b45b22d0862ffee8f.tar.bz2
MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 3e11a468cdf8..54f9e84db8ac 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -43,6 +43,8 @@
#include <linux/io.h>
#include <linux/irq.h>
+#include <asm/cpu.h>
+
/* cpu pipeline flush */
void static inline au_sync(void)
{
@@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
static inline int alchemy_get_cputype(void)
{
- switch (read_c0_prid() & 0xffff0000) {
+ switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
case 0x00030000:
return ALCHEMY_CPU_AU1000;
break;