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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-26 10:45:33 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-26 10:45:33 -0800 |
commit | 89261c57021352045c4af24522c6854c9ee90139 (patch) | |
tree | ad7e2fd28eb7cc6700807b4c6cdc546959563bc8 /arch/mips/include/asm/cpu-features.h | |
parent | c2f1f3e0e17d94ab0c66d83e669492cb9e9a3698 (diff) | |
parent | adcc81f148d733b7e8e641300c5590a2cdc13bf3 (diff) | |
download | linux-89261c57021352045c4af24522c6854c9ee90139.tar.bz2 |
Merge tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton:
"Here's the main MIPS pull for Linux 4.21. Core architecture changes
include:
- Syscall tables & definitions for unistd.h are now generated by
scripts, providing greater consistency with other architectures &
making it easier to add new syscalls.
- Support for building kernels with no floating point support, upon
which any userland attempting to use floating point instructions
will receive a SIGILL. Mostly useful to shrink the kernel & as
preparation for nanoMIPS support which does not yet include FP.
- MIPS SIMD Architecture (MSA) vector register context is now exposed
by ptrace via a new NT_MIPS_MSA regset.
- ASIDs are now stored as 64b values even for MIPS32 kernels,
expanding the ASID version field sufficiently that we don't need to
worry about overflow & avoiding rare issues with reused ASIDs that
have been observed in the wild.
- The branch delay slot "emulation" page is now mapped without write
permission for the user, preventing its use as a nice location for
attacks to execute malicious code from.
- Support for ioremap_prot(), primarily to allow gdb or other ptrace
users the ability to view their tracee's memory using the same
cache coherency attribute.
- Optimizations to more cpu_has_* macros, allowing more to be
compile-time constant where possible.
- Enable building the whole kernel with UBSAN instrumentation.
- Enable building the kernel with link-time dead code & data
elimination.
Platform specific changes include:
- The Boston board gains a workaround for DMA prefetching issues with
the EG20T Platform Controller Hub that it uses.
- Cleanups to Cavium Octeon code removing about 20k lines of
redundant code, mostly unused or duplicate register definitions in
headers.
- defconfig updates for the DECstation machines, including new
defconfigs for r4k & 64b machines.
- Further work on Loongson 3 support.
- DMA fixes for SiByte machines"
* tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (95 commits)
MIPS: math-emu: Write-protect delay slot emulation pages
MIPS: Remove struct mm_context_t fp_mode_switching field
mips: generate uapi header and system call table files
mips: add system call table generation support
mips: remove syscall table entries
mips: add +1 to __NR_syscalls in uapi header
mips: rename scall64-64.S to scall64-n64.S
mips: remove unused macros
mips: add __NR_syscalls along with __NR_Linux_syscalls
MIPS: Expand MIPS32 ASIDs to 64 bits
MIPS: OCTEON: delete redundant register definitions
MIPS: OCTEON: cvmx_gmxx_inf_mode: use oldest forward compatible definition
MIPS: OCTEON: cvmx_mio_fus_dat3: use oldest forward compatible definition
MIPS: OCTEON: cvmx_pko_mem_debug8: use oldest forward compatible definition
MIPS: OCTEON: octeon-usb: use common gpio_bit definition
MIPS: OCTEON: enable all OCTEON drivers in defconfig
mips: annotate implicit fall throughs
MIPS: Hardcode cpu_has_mips* where target ISA allows
MIPS: MT: Remove norps command line parameter
MIPS: Only include mmzone.h when CONFIG_NEED_MULTIPLE_NODES=y
...
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
-rw-r--r-- | arch/mips/include/asm/cpu-features.h | 60 |
1 files changed, 35 insertions, 25 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 0edba3e75747..701e525641b8 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -15,6 +15,7 @@ #include <cpu-feature-overrides.h> #define __ase(ase) (cpu_data[0].ases & (ase)) +#define __isa(isa) (cpu_data[0].isa_level & (isa)) #define __opt(opt) (cpu_data[0].options & (opt)) /* @@ -53,6 +54,18 @@ #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) /* + * Similarly allow for ISA level checks that take into account knowledge of the + * ISA targeted by the kernel build, provided by MIPS_ISA_REV. + */ +#define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) +#define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) +#define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) +#define __isa_range(ge, lt) \ + ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) +#define __isa_range_or_flag(ge, lt, flag) \ + (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) + +/* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems. */ @@ -115,10 +128,15 @@ #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu -#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) -#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) +# ifdef CONFIG_MIPS_FP_SUPPORT +# define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) +# define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) +# else +# define cpu_has_fpu 0 +# define raw_cpu_has_fpu 0 +# endif #else -#define raw_cpu_has_fpu cpu_has_fpu +# define raw_cpu_has_fpu cpu_has_fpu #endif #ifndef cpu_has_32fpr #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) @@ -195,7 +213,9 @@ #endif #ifndef cpu_has_mmips -# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS +# if defined(__mips_micromips) +# define cpu_has_mmips 1 +# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) # else # define cpu_has_mmips 0 @@ -246,48 +266,38 @@ #endif #endif -/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */ -#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \ - (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \ - (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \ - (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \ - (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \ - (defined(cpu_has_mips64r6) && cpu_has_mips64r6)) -#define CPU_NO_EFFICIENT_FFS 1 -#endif - #ifndef cpu_has_mips_1 -# define cpu_has_mips_1 (!cpu_has_mips_r6) +# define cpu_has_mips_1 (MIPS_ISA_REV < 6) #endif #ifndef cpu_has_mips_2 -# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) +# define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) #endif #ifndef cpu_has_mips_3 -# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) +# define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) #endif #ifndef cpu_has_mips_4 -# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) +# define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) #endif #ifndef cpu_has_mips_5 -# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) +# define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) #endif #ifndef cpu_has_mips32r1 -# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) +# define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) #endif #ifndef cpu_has_mips32r2 -# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) +# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) #endif #ifndef cpu_has_mips32r6 -# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) +# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) #endif #ifndef cpu_has_mips64r1 -# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) +# define cpu_has_mips64r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1) #endif #ifndef cpu_has_mips64r2 -# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) +# define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2) #endif #ifndef cpu_has_mips64r6 -# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) +# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) #endif /* |