diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2009-04-19 03:21:22 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-05-14 13:50:26 +0100 |
| commit | 47740eb887796608fb4c629aa6b8507a2fb6c0eb (patch) | |
| tree | 3b772b4b5f3a09899ec27c131cfdace411c75d74 /arch/mips/include/asm/cpu-features.h | |
| parent | 5d57c31e5790d44905af0459a21086dbad167d26 (diff) | |
| download | linux-47740eb887796608fb4c629aa6b8507a2fb6c0eb.tar.bz2 | |
MIPS: Enable CLO / CLZ instructions via separate CPU property
This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do
not implement the full MIPS32 / MIPS64 architecture.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index a0d14f85b781..c0047f861337 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -147,6 +147,15 @@ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) +/* + * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other + * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels + * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. + */ +# ifndef cpu_has_clo_clz +# define cpu_has_clo_clz cpu_has_mips_r +# endif + #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif |