diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2013-08-28 10:41:47 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-03 23:22:18 +0200 |
| commit | 2c4f1ac5623750e715ae2a5fc7e0569999b9bfc5 (patch) | |
| tree | 597a3bd6c681e40174abdafb82ad13e472957753 /arch/mips/ath79/setup.c | |
| parent | 6612a6885b47e73a55d159e5aa4654de89fbfc29 (diff) | |
| download | linux-2c4f1ac5623750e715ae2a5fc7e0569999b9bfc5.tar.bz2 | |
MIPS: ath79: Switch to the clkdev framework
The ath79 code uses static clock devices and
provides its own clk_{get,put} implementations.
Change the code to use dynamically allocated
clock devices and register the clocks within
the clkdev framework.
Additionally, remove the local clk_{get,put}
implementation. The clkdev framework has a
common implementation of those.
Also move the call of ath79_clock_init() from
plat_mem_init() to plat_time_init(). Otherwise
it would not be possible to use memory allocation
functions from ath79clock_init() becasuse the
memory subsystem is not yet initialized when
plat_mem_init() runs.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5780/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath79/setup.c')
| -rw-r--r-- | arch/mips/ath79/setup.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index c02d3459b3ea..64807a4809d0 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -200,7 +200,6 @@ void __init plat_mem_setup(void) ath79_detect_sys_type(); detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - ath79_clocks_init(); _machine_restart = ath79_restart; _machine_halt = ath79_halt; @@ -214,6 +213,8 @@ void __init plat_time_init(void) unsigned long ddr_clk_rate; unsigned long ref_clk_rate; + ath79_clocks_init(); + cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); |