summaryrefslogtreecommitdiffstats
path: root/arch/m68k
diff options
context:
space:
mode:
authorGreg Ungerer <gerg@linux-m68k.org>2016-08-26 15:59:30 +1000
committerGreg Ungerer <gerg@linux-m68k.org>2016-09-26 12:02:58 +1000
commit8cf4a973b47d69227b8ad31d41e4054c59de4dcc (patch)
tree86ce0fcdd765fd108246a91797d3eb7ac8da1f6b /arch/m68k
parentf71160655d1efda10081482c486481f2108abca5 (diff)
downloadlinux-8cf4a973b47d69227b8ad31d41e4054c59de4dcc.tar.bz2
m68k: generalize io memory region setup for ColdFire ACR registers
The ACR registers of the ColdFire define at a macro level what regions of the addresses space should have caching or other attribute types applied. Currently for the MMU enabled setups we map the interal IO peripheral addres space as uncachable based on the define for the MBAR address (CONFIG_MBAR). Not all ColdFire SoC use a programmable MBAR register address. Some parts have fixed addressing for their internal peripheral registers. Generalize the way we get the internal peripheral base address so all types can be accomodated in the ACR definitions. Each ColdFire SoC type now sets its IO memory base and size definitions (which may be based on MBAR) which are then used in the ACR definitions. Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/include/asm/m5441xsim.h2
-rw-r--r--arch/m68k/include/asm/m54xxacr.h2
-rw-r--r--arch/m68k/include/asm/m54xxsim.h2
3 files changed, 5 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
index 4279c0df0844..64f60be47066 100644
--- a/arch/m68k/include/asm/m5441xsim.h
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -12,6 +12,8 @@
#define MCF_BUSCLK (MCF_CLK / 2)
#define MACHINE MACH_M5441X
#define FPUTYPE 0
+#define IOMEMBASE 0xe0000000
+#define IOMEMSIZE 0x20000000
#include <asm/m54xxacr.h>
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 59e171063c2f..c6ac05cda282 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -94,7 +94,7 @@
* register region as non-cacheable. And then we map all our RAM as
* cacheable and supervisor access only.
*/
-#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
+#define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 7dd6cc4bcd72..73d937ff36eb 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -10,6 +10,8 @@
#define MCF_BUSCLK (MCF_CLK / 2)
#define MACHINE MACH_M54XX
#define FPUTYPE FPU_COLDFIRE
+#define IOMEMBASE MCF_MBAR
+#define IOMEMSIZE 0x01000000
#include <asm/m54xxacr.h>