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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-10 08:38:57 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-10 08:38:57 -0800
commitecb50f0afd35a51ef487e8a54b976052eb03d729 (patch)
tree27457f87d3dc2ce6c81e16d795f953e66c2fff45 /arch/arm
parenta157508c9790ccd1c8b5c6a828d6ba85bbe95aaa (diff)
parent1655b0530d9502e69686220491ffb15ba0738c58 (diff)
downloadlinux-ecb50f0afd35a51ef487e8a54b976052eb03d729.tar.bz2
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq core updates from Thomas Gleixner: "This is the first (boring) part of irq updates: - support for big endian I/O accessors in the generic irq chip - cleanup of brcmstb/bcm7120 drivers so they can be reused for non ARM SoCs - the usual pile of fixes and updates for the various ARM irq chips" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip: dw-apb-ictl: Add PM support irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed ARM: orion: convert the irq_reg_{readl,writel} calls to the new API irqchip: atmel-aic: Add missing entry for rm9200 irq fixups irqchip: atmel-aic: Rename at91sam9_aic_irq_fixup for naming consistency irqchip: atmel-aic: Add specific irq fixup function for sam9g45 and sam9rl irqchip: atmel-aic: Add irq fixups for at91sam926x SoCs irqchip: atmel-aic: Add irq fixup for RTT block irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Decouple driver from brcmstb-l2 irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask irqchip: bcm7120-l2: Make sure all register accesses use base+offset irqchip: bcm7120-l2, brcmstb-l2: Remove ARM Kconfig dependency irqchip: bcm7120-l2: Eliminate bad IRQ check irqchip: brcmstb-l2: Eliminate dependency on ARM code genirq: Generic chip: Add big endian I/O accessors ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-bcm/Kconfig1
-rw-r--r--arch/arm/plat-orion/gpio.c8
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 1bd39b45d08b..aaeec78c3ec4 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -143,6 +143,7 @@ config ARCH_BRCMSTB
select HAVE_ARM_ARCH_TIMER
select BRCMSTB_GISB_ARB
select BRCMSTB_L2_IRQ
+ select BCM7120_L2_IRQ
help
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
chipset.
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index e048f6198d68..14f6e647c739 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -505,9 +505,9 @@ static void orion_gpio_unmask_irq(struct irq_data *d)
u32 mask = d->mask;
irq_gc_lock(gc);
- reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+ reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val |= mask;
- irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+ irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}
@@ -519,9 +519,9 @@ static void orion_gpio_mask_irq(struct irq_data *d)
u32 reg_val;
irq_gc_lock(gc);
- reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
+ reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val &= ~mask;
- irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
+ irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}