diff options
author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:34 +0000 |
---|---|---|
committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:16 +0000 |
commit | 8a950efa1ff0393967d79428b16af88193591ab3 (patch) | |
tree | ef8bd210362894db0020237041a80dd86128ab9c /arch/arm64 | |
parent | f70a810e01b2ad7eaad3470be1cf4220249bb251 (diff) | |
download | linux-8a950efa1ff0393967d79428b16af88193591ab3.tar.bz2 |
arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
Convert ID_MMFR5_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-36-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/include/asm/sysreg.h | 3 | ||||
-rw-r--r-- | arch/arm64/tools/sysreg | 12 |
2 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index aabc6db300fa..25e96aa84ae8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -168,7 +168,6 @@ #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) -#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) @@ -679,8 +678,6 @@ #define ID_DFR1_EL1_MTPMU_SHIFT 0 -#define ID_MMFR5_EL1_ETS_SHIFT 0 - #define ID_DFR0_EL1_PerfMon_SHIFT 24 #define ID_DFR0_EL1_MProfDbg_SHIFT 20 #define ID_DFR0_EL1_MMapTrc_SHIFT 16 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f0481f626405..e83816c175a4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -717,6 +717,18 @@ Enum 3:0 CSV3 EndEnum EndSysreg +Sysreg ID_MMFR5_EL1 3 0 0 3 6 +Res0 63:8 +Enum 7:4 nTLBPA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 ETS + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64PFR0_EL1 3 0 0 4 0 Enum 63:60 CSV3 0b0000 NI |