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authorWill Deacon <will@kernel.org>2021-06-24 14:07:04 +0100
committerWill Deacon <will@kernel.org>2021-06-24 14:07:04 +0100
commit3d1bf78c7b13a0ad88e77dce94df88400f47e0dd (patch)
tree8175a9c64a9dbfb47f73dd059a9f8233a1ce14ff /arch/arm64/mm/context.c
parenta4a49140ae84e74f5d831c2416fe4860c8ff9d34 (diff)
parentad4711f962e08eff8d6e9b03f9670b1af6ea9395 (diff)
downloadlinux-3d1bf78c7b13a0ad88e77dce94df88400f47e0dd.tar.bz2
Merge branch 'for-next/sve' into for-next/core
Optimise SVE switching for CPUs with 128-bit implementations. * for-next/sve: arm64/sve: Skip flushing Z registers with 128 bit vectors arm64/sve: Use the sve_flush macros in sve_load_from_fpsimd_state() arm64/sve: Split _sve_flush macro into separate Z and predicate flushes
Diffstat (limited to 'arch/arm64/mm/context.c')
0 files changed, 0 insertions, 0 deletions