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| author | Alexandru Elisei <alexandru.elisei@arm.com> | 2021-06-18 11:51:39 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2021-06-18 13:23:50 +0100 |
| commit | 2a71fabf6a1bc9162a84e18d6ab991230ca4d588 (patch) | |
| tree | e4fe0dd7f6022ca1a496c85aa04e5bb2e7f39482 /arch/arm64/kvm/pmu-emul.c | |
| parent | 8124c8a6b35386f73523d27eacb71b5364a68c4c (diff) | |
| download | linux-2a71fabf6a1bc9162a84e18d6ab991230ca4d588.tar.bz2 | |
KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:
"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."
Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com
Diffstat (limited to 'arch/arm64/kvm/pmu-emul.c')
| -rw-r--r-- | arch/arm64/kvm/pmu-emul.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index fd167d4f4215..ecc0d19c8cc1 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); if (val & ARMV8_PMU_PMCR_P) { + mask &= ~BIT(ARMV8_PMU_CYCLE_IDX); for_each_set_bit(i, &mask, 32) kvm_pmu_set_counter_value(vcpu, i, 0); } |